The dominant computational resource is not time or memory but energy in current IT systems ranging from embedded to HPC systems. Novel execution models that allow for holistic optimisation across all the layers of the system stack has been shown to be capable to yield orders of magnitude improvements in power efficiency . The execution models not only model energy and performance at various levels of abstraction but also explicitly express the key factors in both embedded and HPC computing (e.g. heterogeneity, data locality, parallelism and overhead), enabling the synthesis of embedded and HPC computing. However developing models and tools to allow software engineers to program energy efficiently and to reason abstractly about power and energy still poses many challenges, which are currently tackled in several research projects . The workshop will provide a platform for open discussion of ongoing research with interested attendees from industry and academia. The workshop is open and free to attend.
Approaches to energy efficient computing paradigms for emerging many-core architectures will be addressed. Workshop topics include, but are not limited to:
- Energy-aware execution models
- Energy efficient algorithms and data structures
- Energy efficient interprocess synchronization
- Energy efficiency in transactional memory
- Energy consumption and fault-tolerance
- Energy-aware compiler optimizations and runtime support
If you wish to participate in the event please send an email before 23-Aug-2016 that includes your name and affiliation to:
Ivan Walulya, ivanw(@)chalmers(.)se.
We wish to encourage attendees and early researchers to showcase their work-in-progress through posters. Submissions should be sent in a single page that includes the title and extended abstract for the poster. We request prospective presenters to email the abstract of their poster to the organizers before August 21st.
|09:05 - 09:10||Welcome talk
-- Philippas Tsigas (CTH) Slides
|09:10 - 09:40|| Invited: Haswell Energy Characterization using Dynamic and Static Power Modeling
-- Sally Mckee, Bhavishya Goel (CTH) Slides
|09:40 - 10:10||Programming frameworks and optimized software composition for parallel systems.
-- Christoph Kessler (LiU) Slides
|10:10 - 10:30||Coffee Break|
|10:30 - 11:00||ICE: A General and Validated Energy Complexity Model for Multi-threaded Algorithms
-- Vi Tran (UiT)Slides
|11:00 - 11:30||Throughput Based Energy Efficiency Modelling and Analysis of Lock-Free Data Structures
-- Aras Atalar (CTH) Slides
|11:30 - 12:00||Monitoring of HPC and Embedded Systems
-- Dennis Hoppe (HLRS) Slides
|12:00 - 13:30||Lunch break|
|13:30 - 14:00||Invited: ICT and Power; How to save $20BN
-- Peter Brauer, David Engdal, Martin Lundqvist (Ericsson AB) Slides
|14:00 - 14:30|| Energy-aware Scheduling with StarPU
-- Fangli Pi (HLRS) Slides
|14:30 - 15:00|| High Performance, Low Power, CNN implementation on Ultra-Low Power embedded platforms
--Brendan Barry (Movidius) Slides
|15:00 - 15:30|| Software infrastructures for energy-efficient execution on heterogeneous parallel systems.
-- Lu Li (LiU) Slides
|15:30 - 16:00||Coffee break|
|16:00 - 16:30|| Energy Efficient Data Stream Processing on Ultra-Low-Power Embedded Multicore Devices.
-- Ivan Walulya (CTH) Slides
|16:30 - 17:00|| SkePU2
-- August Ernstsson (LiU) Slides
|17:00 - 17:30||Closing Panel Discussion|
Aras Atalar, aaras(@)chalmers(.)se
Philippas Tsigas, philippas.tsigas(@)chalmers(.)se
Ivan Walulya, ivanw(@)chalmers(.)se
Room : Afrodite
(The Science Park Conference center), Sven Hultins gata 9 412 58 Göteborg
Chalmers University of Technology. Teknikparkens Konferenscenter is located at Johanneberg Science Park in the southern area of Chalmers University of Technology. It is easy to get here by tram, bus or car.